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CPU cache
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#	Item
291	Defending Against Attacks on Main Memory Persistence∗ William Enck, Kevin Butler, Thomas Richardson, Patrick McDaniel, and Adam Smith Systems and Internet Infrastructure Security (SIIS) Laboratory, Department of Comput Add to Reading List Source URL: www.enck.org Language: English CPU cache Computer data storage Dynamic random-access memory Direct memory access Memory hierarchy Solid-state drive Cache Random-access memory Microarchitecture Computer hardware Computer memory Computing
292	Fractal Prefetching B+-Trees: Optimizing Both Cache and Disk Performance Shimin Chen, Phillip B. Gibbonsy , Todd C. Mowry, and Gary Valentinx School of Computer Science Carnegie Mellon University Pittsburgh, PA 15213 Add to Reading List Source URL: www.pdl.cmu.edu Language: English - Date: 2002-04-19 11:52:33 Graph theory Binary trees R-tree B+ tree T-tree CPU cache Trie Linked list Cache B-tree Computing Data management
293	How to Improve Cache Performance? CS252 Graduate Computer Architecture Lecture 7 Add to Reading List Source URL: www.cs.berkeley.edu Language: English - Date: 2003-06-11 14:31:47 Computing Computer architecture Cache CPU cache Translation lookaside buffer Alpha 21164 Write buffer Acumem SlowSpotter R8000 Computer hardware Computer memory Central processing unit
294	A Cost Framework for Evaluating Integrated Restructuring Optimizations Bharat Chandramouli, John B. Carter, Wilson C. Hsieh, Sally A. McKee School of Computing University of Utah Abstract Add to Reading List Source URL: research.ac.upc.edu Language: English - Date: 2002-03-20 08:47:59 Computer programming Programming language theory Loop optimization CPU cache Lookup table Aliasing Cache Row-major order Dynamic array Computing Compiler optimizations Arrays
295	Adaptive Mode Control: A Static-Power-Efficient Cache Design Huiyang Zhou, Mark C. Toburen, Eric Rotenberg, Thomas M. Conte Department of Electrical and Computer Engineering North Carolina State University {hzhou, mctobu Add to Reading List Source URL: research.ac.upc.edu Language: English - Date: 2002-03-20 08:47:54 Cache Central processing unit CPU cache Lookup table Dynamic random-access memory Cache algorithms Computing Computer memory Computer hardware
296	´ Ecole Polytechnique F´ ed´ erale de Lausanne, Switzerland Add to Reading List Source URL: www.tuxmaniac.com Language: English - Date: 2010-01-19 05:45:28 Cache coherency Parallel computing Computer memory Microprocessors Central processing unit CPU cache Multi-core processor MESI protocol Cache coherence Computing Computer hardware Computer architecture
297	METAMOC: MODULAR EXECUTION TIME ANALYSIS USING MODEL CHECKING Andreas E. Dalsgaard1, Mads Chr. Olesen1, Martin Toft1, Ren´e R. Hansen1, Kim G. Larsen1 Abstract Safe and tight worst-case execution times (WCETs) are impor Add to Reading List Source URL: people.cs.aau.dk Language: English - Date: 2012-10-25 20:25:12 Central processing unit Instruction set architectures Classes of computers CPU cache Computer memory Worst-case execution time ARM9 Cache Microarchitecture Computer architecture Computing Computer hardware
298	Physical Simulation for Animation and Visual Effects: Parallelization and Characterization for Chip Multiprocessors ∗ Christopher J. Hughes†, Radek Grzeszczuk‡ , Eftychios Sifakis§∗, Add to Reading List Source URL: pages.cs.wisc.edu Language: English - Date: 2010-09-08 13:38:12 Spaceflight Concurrent computing Application programming interfaces Computer memory Compiler optimizations Multi-core processor CPU cache OpenMP Automatic parallelization Computing Parallel computing Computer programming
299	Toward Predictable Performance in Software Packet-Processing Platforms Mihai Dobrescu EPFL, Switzerland Katerina Argyraki Add to Reading List Source URL: www.eecs.berkeley.edu Language: English - Date: 2012-11-24 04:26:29 Microprocessors CPU cache Central processing unit Computer memory Electronics Multi-core processor Packet Processing Xeon Transmission Control Protocol Computing Computer hardware Cache
300	The University of Hertfordshire The Challenges facing Libraries and Imperative Languages from Massively Parallel Architectures Jason McGuiness Add to Reading List Source URL: accu.org Language: English - Date: 2008-04-14 03:49:41 Central processing unit Parallel computing Classes of computers Microprocessors Instruction-level parallelism Superscalar Very long instruction word CPU cache Instruction set Computer architecture Computing Computer hardware

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